Output signal generation in the form of output buffers is an integral part of electronics. A very common use is in, for example, clock generators. Their use is wide and diverse. Clocks are used for circuit control, to keep track of time, etc. Within the personal computer clocks are used by a variety of logic blocks including, but not limited to, for example, the central processor unit (CPU), as bus clocks, clocks for system chip sets, driving memories, etc. Additionally they are used to synchronize events and provide a reliable source of a stable frequency.
For example, FIG. 3 illustrates an approach 300 showing a clock, and several system components. Here, clock 302 supplies a frequency to the system chip set 304 which in turn is providing a signal to buffer 306 which drives via 306-1 and 306-2 a DIMM (dual inline memory module) 308. Thus buffer 306 is driving the memory. Because of the increasing memory speeds, variation in memory module layout, for example on a motherboard (or orientation of the DIMM modules themselves), variation in signal path length, etc. timing issues, such as signal delay, may arise. To provide some indication of signal delay and to try an compensate for this delay, signal 302-2 is also fed back to system chip set 304. The system chip set 304 may try and compensate for delays, however, as shown there is no feedback from 306-1 to try and compensate for delays in this path. This may present a problem.
FIG. 4 shows another approach where each smaller group of signals has one dedicated feedback path. Shown for simplicity is only a clock 402, a PLL 404-1, and 404-2, the outputs 406-1, 406-2, and feedback 408-1, and 408-2. While the PLL has multiple output, here at 406 a group of 6 signals, it will be noted that only 1 is providing feedback to the respective PLL. Six clock signals may be used, for example, when driving a DRAM (dynamic random access memory) Module using three clock pairs. It is understood by one of skill in the art that the PLL may be used to align the respective outputs 406 with the input clock reference 402 by using the feedback 408. It should be noted that if taken to the extreme limit, this approach has a single PLL for each output. This would allow complete adjustment of each output, however this approach may be expensive which presents a problem.